Allwinner /D1H /UART[5] /LSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dr)dr 0 (oe)oe 0 (pe)pe 0 (fe)fe 0 (bi)bi 0 (thre)thre 0 (temt)temt 0 (fifoerr)fifoerr

Description

UART Line Status Register

Fields

dr

Data Ready

1 (ready): undefined

oe

Overrun Error

1 (error): undefined

pe

Parity Error

1 (error): undefined

fe

Framing Error

1 (error): undefined

bi

Break Interrupt

thre

TX Holding Register Empty

1 (empty): undefined

temt

Transmitter Empty

1 (empty): undefined

fifoerr

RX Data Error in FIFO

1 (error): undefined

Links

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